The present invention relates generally to a semiconductor apparatus, and more particularly, to a semiconductor apparatus and a data write circuit of a semiconductor apparatus.
FIG. 1 is a circuit diagram showing a data write circuit of a semiconductor apparatus according to the related art.
Referring to FIG. 1, The data write circuit of the semiconductor integrated circuit according to the related art includes pre-patch unit 2, first to fourth multiplexers 11 to 14, first to fourth latches 15 to 18, and first to fourth drivers 19 to 22.
The pre-patch unit 2 can be composed of pipe-latch which comprises buffer and a plurality of latches. The pre-patch unit 2 generates parallel data D0 to D3 by latching data inputted serially.
The pre-patch unit 2 pre-patches the data D0 to D3 in response to signals DQSR and DQSF synchronized with a rising edge and a falling edge of a data strobe signal DQS.
Each of the first to fourth multiplexers 11 to 14 can selectively output data D0 to D3 according to first selection signals SOSEB<0:3> and second selection signals SSEL<0:3>.
The first to fourth latches 15 to 18 latch the output signals ‘DINR0’, DINF0’, ‘DINR1’, and ‘DINF1’ of the first to fourth multiplexers 11 to 14, respectively, according to a data clock signal ‘DCLK’.
The first to fourth drivers 19 to 22 drive the output signals of the first to fourth latches 15 to 18 and transmit the signals to global input/output lines ‘GIO_Q0’ to GIO_Q3’.
FIG. 2 is a timing chart shown for illustrating the operation of the data write circuit shown in FIG. 1.
Referring to FIG. 2, in the data write circuit according to the related art, the signals ‘DINR0’, ‘DINF0’, ‘DINR1’, and ‘DINF1’ that are output by the first to fourth multiplexers 11 to 14 are simultaneously carried to the global input/output lines ‘GIO_Q0’ to ‘GIO_Q3’ in accordance with the data clock signal ‘DCLK’.
FIG. 2 shows an example of when four data D0 to D3 are carried to the corresponding global input/output lines ‘GIO_Q0’ to ‘GIO_Q3’. In actuality, a very large number of the global input/output lines will exist. For example, 64 global input/output lines exist in the case of DDR2, and 128 global input/output lines exist in the case of DDR3, and data is simultaneously carried to the very large number of global data lines.
Typically, when the size of a semiconductor apparatus is decreased, the ratio of global data lines to the entire area of the semiconductor apparatus increases and the width of the global data line is narrowed. Consequently, the distance between adjacent global data lines decreases.
When a large amount of data is simultaneously carried to the global input/output lines, the data carried in adjacent global input/output lines will often have different logical levels.
When the data carried in adjacent global input/output lines have opposite logical levels, a data transmission delay is caused by an increase in a parasitic capacitance that is generated by a coupling effect between the data. As a consequence, the transmission characteristics of the semiconductor apparatus are deteriorated and it is possible for errors to be caused during the operation of the semiconductor apparatus.